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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad5260/ad5262 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 1-/2-channel 15 v digital potentiometers features 256 positions ad5260 C 1-channel ad5262 C 2-channel (independently programmable) potentiometer replacement 20 k , 50 k , 200 k low temperature coefficient 35 ppm/ c 4-wire spi-compatible serial data input 5 v to 15 v single-supply; 5.5 v dual-supply operation power on mid-scale preset applications mechanical potentiometer replacement instrumentation: gain, offset adjustment stereo channel audio level control programmable voltage to current conversion programmable filters, delays, time constants line impedance matching low resolution dac replacement general description the ad5260/ad5262 provide a single- or dual-channel, 256- position, digitally controlled variable resistor (vr) device. * these devices perform the same electronic adjustment function as a potentiometer or variable resistor. each channel of the ad5260/ ad5262 contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point determined by a digital code loaded into the spi-compatible serial-input register. the resistance between the wiper and either end point of the fixed resistor varies linearly with respect to the digital code transferred into the vr latch. the variable resistor offers a completely programmable value of resistance, between the a terminal and the wiper or the b terminal and the wiper. the fixed a to b terminal resistance of 20 k w , 50 k w , or 200 k w has a nominal temperature coefficient of 35 ppm/ c. unlike the majority of the digital potentiometers in the market, these devices can operate up to 15 v or 5 v provided proper supply voltages are furnished. each vr has its own vr latch, which holds its programmed resistance value. these vr latches are updated from an internal serial-to-parallel shift register, which is loaded from a standard 3-wire serial-input digital interface. the ad5260 contains an 8-bit serial register while the ad5262 contains a 9-bit serial register. each bit is clocked into the register on the positive edge of the clk. the ad5262 address bit determines the corresponding vr latch to be loaded with the last 8 bits of the data word during the positive edging of cs strobe. a serial data output pin at the opposite end of the serial register enables simple daisy chaining in multiple vr applications without additional external decoding logic. an optional reset pin ( pr ) forces the wiper to the mid-scale position by loading 80 h into the vr latch. * the terms digital potentiometers, vr, and rdac are used interchangeably. functional block diagrams rdac register logic 8 power-on reset serial input register ad5260 s hdn v dd cs clk sdi gnd awb sdo pr v ss v l rdac1 register logic 8 ad5262 s hdn v dd v ss clk sdi gnd rdac2 register a1 w1 b1 v l cs sdo pr a2 w2 b2 power-on reset serial input register r wb r wa code ? decimal 100 064128 192 256 percent of nominal end-to-end resistance ? % r ab 75 50 25 0 figure 1. r wa and r wb vs. code the ad5260/ad5262 are available in thin surface-mount tssop-14 and tssop-16 packages. all parts are guaranteed to operate over the extended industrial temperature range of ?0 c to +85 c.
rev. 0 ?2? ad5260/ad5262especifications (v dd = +15 v, v ss = 0 v or, v dd = +5 v, v ss = e5 v, v l = +5 v, v a = +5 v, v b = 0 v, e 40 c < t a < +85 c unless otherwise noted.) electrical characteristics 20 k w , 50 k w , 200 k w versions parameter symbol conditions min typ 1 max unit dc characteristics rheostat mode specifications apply to all vrs resistor differential nl 2 r-dnl r wb , v a =nc e1 1/4 +1 lsb resistor nonlinearity 2 r-inl r wb , v a =nc e1 1/2 +1 lsb nominal resistor tolerance 3 w channel resistance matching (ad5262 only) 1/4 +1 lsb integral nonlinearity 4 inl e1 1/2 +1 lsb voltage divider temperature coefficient d v w / d tc ode = 80 h 5 ppm/ m a digital inputs and outputs input logic high v ih 2.4 v input logic low v il 0.8 v input logic high v ih v l = 3 v, v ss = 0 v 2.1 v input logic low v il v l = 3 v, v ss = 0 v 0.6 v output logic high (sdo) v oh r pull-up = 2 k w to 5 v 4.9 v output logic low (sdo) v ol i ol = 1.6 ma, v logic = 5 v 0.4 v input current 8 i il v in = 0 v or 5 v 1 m a input capacitance 6 c il 5pf power supplies logic supply v l 2.7 5.5 v power single-supply range v dd range v ss = 0 v 4.5 16.5 v power dual-supply range v dd/ss range 4.5 5.5 v logic supply current i l v l =5 v 60 m a positive supply current i dd v ih = 5 v or v il = 0 v 1 m a negative supply current i ss v ss = e5 v 1 m a power dissipation 9 p diss v ih = 5 v or v il = 0 v, 0.3 mw v dd = +5 v, v ss = e5 v power supply sensitivity pss d v dd = +5 v, 10% 0.003 0.01 %/% dynamic characteristics 6, 10 bandwidth e3 db bw r ab = 20 k w /50 k w /200 k w 310/130/30 khz total harmonic distortion thd w v a = 1 v rms , v b = 0 v, 0.014 % f=1 khz, r ab = 20 k w v w settling time t s v a = +5 v, v b = e5 v, 5 m s 1 lsb error band, r ab = 20 k w crosstalk 11 c t v a = v dd , v b =0 v, measure v w with adjacent rdac making full-scale 1 nves code change (ad5262 only) analog crosstalk c ta v a1 = v dd , v b1 = 0v, measure v w1 w ith v w2 = 5 v p-p @ f = 10 khz, e64 db r ab = 20 k w /200 k w (ad5262 only) resistor noise voltage e n_wb r wb = 20 k w 13 nv/ hz f = 1 khz
rev. 0 C3C ad5260/ad5262 parameter symbol conditions min typ max unit interface timing characteristics apply to all parts 6, 12 clock frequency f clk 25 mhz input clock pulsewidth t ch , t cl clock level high or low 20 ns data setup time t ds 10 ns data hold time t dh 10 ns clk to sdo propagation delay 13 t pd r l = 1 k ? , c l < 20pf 1 160 ns cs setup time t css 5ns cs high pulsewidth t csw 20 ns reset pulsewidth t rs 50 ns clk fall to cs rise hold time t csh 0ns cs rise to clock rise setup t cs1 10 ns notes the ad5260/ad5262 contains 1,968 transistors. die size: 89 mil. 105 mil. 9,345 sq. mil. 1 typicals represent average readings at 25 c and v dd = +5 v, v ss = C5 v. 2 resistor position nonlinearity error r-inl is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic. i w = v dd /r for both v dd = +5 v, v ss =C5v. 3 v ab = v dd , wiper (v w ) = no connect. 4 inl and dnl are measured at v w with the rdac configured as a potentiometer divider similar to a voltage output d/a converter. va = v dd and v b = 0v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. 5 resistor terminals a, b, w have no limitations on polarity with respect to each other. 6 guaranteed by design and not subject to production test. 7 measured at the ax terminals. all ax terminals are open-circuit in shutdown mode. 8 worst-case supply current consumed when input all logic-input levels set at 2.4 v, standard characteristic of cmos logic. 9 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 10 all dynamic characteristics use v dd = +5 v, v ss = C5 v, v l = +5 v. 11 measured at a v w pin where an adjacent v w pin is making a full-scale voltage change. 12 see timing diagram for location of measured values. all input control voltages are specified with t r =t f = 2ns (10% to 90% of 3 v) and timed from a voltage level of 1.5 v. switching characteristics are measured using v l = 5 v. 13 propagation delay depends on value of v dd , r l , and c l . specifications subject to change without notice. absolute maximum ratings 1 (t a = 25 c, unless otherwise noted.) v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v, +15 v v ss to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v, C7 v v dd to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 v v a , v b , v w to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . v ss , v dd a x C b x , a x C w x , b x C w x intermittent 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ma continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ma digital inputs and output voltage to gnd . . . . . . . 0 v, 7 v operating temperature range . . . . . . . . . . . . C40 c to +85 c maximum junction temperature (t j max ) . . . . . . . . . . . 150 c storage temperature . . . . . . . . . . . . . . . . . . C65 c to +150 c lead temperature (soldering, 10 sec) . . . . . . . . . . . . 300 c vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c thermal resistance 3 ja tssop-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 c/w tssop-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 c/w notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the a, b, and w terminals at a given resistance setting. 3 package power dissipation = (t j max C t a )/ ja
rev. 0 ?4? ad5260/ad5262 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad5260/ad5262 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device ordering guide package package no. of parts branding model r ab (k w ) temperature description option per container information * ad5260bru20 20 ?0 c to +85 ct ssop-14 ru-14 96 ad5260b20 ad5260bru20-reel7 20 ?0 c to +85 ct ssop-14 ru-14 1000 ad5260b20 ad5260bru50 50 ?0 c to +85 ct ssop-14 ru-14 96 ad5260b50 ad5260bru50-reel7 50 ?0 c to +85 ct ssop-14 ru-14 1000 ad5260b50 ad5260bru200 200 ?0 c to +85 ct ssop-14 ru-14 96 ad5260b200 ad5260bru200-reel7 200 ?0 c to +85 ct ssop-14 ru-14 1000 ad5260b200 ad5262bru20 20 ?0 c to +85 ct ssop-16 ru-16 96 ad5262b20 ad5262bru20-reel7 20 ?0 c to +85 ct ssop-16 ru-16 1000 ad5262b20 ad5262bru50 50 ?0 c to +85 ct ssop-16 ru-16 96 ad5262b50 ad5262bru50-reel7 50 ?0 c to +85 ct ssop-16 ru-16 1000 ad5262b50 ad5262bru200 200 ?0 c to +85 ct ssop-16 ru-16 96 ad5262b200 ad5262bru200-reel7 200 ?0 c to +85 ct ssop-16 ru-16 1000 ad5262b200 * line 1 contains part number, line 2 contains differentiating detail by part type and adi logo symbol, line 3 contains date code yww.
rev. 0 ?5? ad5260/ad5262 t able i. ad5260 8-bit serial-data word format data b7 b6 b5 b4 b3 b2 b1 b0 d7 d6 d5 d4 d3 d2 d1 d0 msb lsb 2 7 2 0 clk 1 0 v out 1 0 rdac register load cs d d d d d d d d sd dd rdcreserld d d d d d d d d cl cs sd dd table ii. ad5262 9-bit serial-data word format addr data b8 b7 b6 b5 b4 b3 b2 b1 b0 a0 d7 d6 d5 d4 d3 d2 d1 d0 msb lsb 2 8 2 7 2 0 sdi (data in) sdo (data out) 1 0 1 0 1 0 1 0 v dd 0v clk cs rd d x or d xd x t css t dh t pd_max 1 lsb error band 1 lsb t csh t ch t csw t s t cl t ds t cs1 figure 2c. detail timing diagram pr dd rs 1 lsb error band 1 lsb t s figure 2d. preset timing diagram
rev. 0 ?6? ad5260/ad5262 ad5260 pin configuration top view (not to scale) 1 2 3 4 5 6 7 a w b v dd shdn cl sd sd l ss d nc nd pr cs ad5260 pin function descriptions pin number mnemonic description 1a a terminal 2w wiper terminal 3b b terminal 4v dd positive power supply, specified for operation at both 5 v or 15 v. (sum of |v dd | + |v ss | 15 v) 5 shdn active low input. terminal a open- circuit. shutdown controls. variable resistors of rdac. 6 clk serial clock input, positive edge triggered. 7 sdi serial data input 8 cs chip select input, active low. when cs returns high, data will be loaded into the rdac register. 9 pr active low preset to mid-scale; sets rdac registers to 80 h . 10 gnd ground 11 v ss negative power supply, specified for operation from 0 v to ? v. 12 v l logic supply voltage, needs to be same voltage as the digital logic controlling the ad5260. 13 nc no connect (users should not connect anything other than dummy pad on this pin) 14 sdo serial data output, open drain transistor requires pull-up resistor. ad5262 pin configuration top view (not to scale) 1 2 3 4 5 6 7 8 a2 a1 w1 v dd shdn cl sd sd l ss d nd pr cs dpnncndescrpns p n d 1s do serial data output, open drain transistor requires pull-up resistor. 2a 1a terminal rdac #1 3w 1 wiper rdac #1, address a0 = 0 2 4b 1b terminal rdac #1 5v dd positive power supply, specified for operation at both 5 v or 15 v. (sum of |v dd |+|v ss | 15 v) 6 shdn active low input. terminal a open-circuit. shutdown controls variable resistors #1 through #2. 7 clk serial clock input, positive edge triggered. 8 sdi serial data input. 9 cs chip select input, active low. when cs returns high, data in the serial input register is decoded, based on the address bit a 0 , and loaded into the target rdac register. 10 pr active low preset to mid-scale sets rdac registers to 80 h . 11 gnd ground 12 v ss negative power supply, specified for operation at both 0 v or ? v (sum of |v dd | + |v ss | <15 v). 13 v l logic supply voltage, needs to be same voltage as the digital logic controlling the ad5262. 14 b2 b terminal rdac #2 15 w2 wiper rdac #2, address a0 = 1 2 16 a2 a terminal rdac #2
rev. 0 ?7? ad5260/ad5262 theory of operation the ad5260/ad5262 provide a single- or dual-channel, 256-position digitally controlled variable resistor (vr) device and operate up to 15 v maximum voltage. changing the programmed vr settings is accomplished by clocking an 8-/9-bit serial data word into the sdi (serial data input) pin. for the ad5262, the format of this data word is one address bit. a0 represents the first bit b8, then followed by eight data bits b7?0 with msb first. tables i and ii provide the serial register data word format. see table iii for the ad5262 address assignment to decode the location of the vr latch receiving the serial register data in bits b7 through b0. vr outputs can be changed one at a time in random sequence. the ad5260/ ad5262 presets to a mid-scale, simplifying fault condition recov- ery at power-up. mid-scale can also be achieved at any time by asserting the pr pin. both parts have an internal power on preset that places the wiper in a mid-scale preset condition at power on. operation of the power on preset function depends only on the state of the v l pin. the ad5260/ad5262 contains a power shutdown shdn pin, which places the rdac in an almost zero power consumption state where terminals ax are open circuited, and the wiper w is con- nected to b, resulting in only leakage currents being consumed in the vr structure. in the shutdown mode, the vr latch settings are maintained so that, returning to operational mode from power shutdown, the vr settings return to their previous resistance values. table iii. ad5262 address decode table a0 latch loaded 0 rdac#1 1 rdac#2 digital interfacing the ad5260/ad5262 contains a 4-wire spi-compatible digital i nterface (sdi, sdo, cs , and clk). for the ad5260, the 8-bit serial word must be loaded with msb first, and the format of the word is shown in table i. for the ad5262, the 9-bit serial word must be loaded with address bit a0 first, then msb of the data. the format of the word is shown in table ii. a0 ser reg d7 d6 d5 d4 d3 d2 d1 d0 a1 w1 b1 v dd cs cl sd nd rdc lch rdc lch pr ss pr sd l shdn per n prese en ddr dec pr dd the positive-edge sensitive clk input requires clean transitions to avoid clocking incorrect data into the serial input register. standard logic families work well. if mechanical switches are used for product evaluation, they should be debounced by a flip-flop or other suitable means. figure 3 shows more detail of the internal digital circuitry. when cs is low, the clock loads data into the serial register on each positive clock edge (see table iv). table iv. truth table clk cs pr shdn register activity ll hh no sr effect, enables sdo pin lh hs hift one bit in from the sdi pin. the eighth previously entered bit is shifted out of the sdo pin. x hh load sr data into rdac latch xh hh no operation xx lh sets all rdac latches to mid-scale, wiper centered, and sdo latch cleared. xh hl atches all rdac latches to 80 h . xh hl open circuits all resistor a?ermi nals, connects w to b, turns off sdo output transistor. * = positive edge, x = don? care, sr = shift register the data setup and data hold times in the specification table determine the data valid time requirements. the ad5260 uses an 8-bit serial input data register word that is transferred to the internal rdac register when the cs line returns to logic high. for the ad5262 the last 9 bits of the data word entered into the serial register are held when cs returns high. any extra bits are ignored. at the same time cs goes high, it gates the address decoder enabling ad5262 one of two positive edge-triggered ad5262 rdac latches (see figure 4). rdac 1 rdac 2 ad5260/ad5262 sdi clk cs ddr decde serl reser ecl the target rdac latch is loaded with the last 8 bits of the serial data word completing one rdac update. for the ad5262, two separate 9-bit data words must be clocked in to change both vr settings. during shutdown ( shdn ) the sdo output pin is forced to the off (logic high state) to disable power dissipation in the pull-up resistor. see figure 5 for equivalent sdo output circuit schem atic. sdi clk cs shdn pr serl reser d c rs sd dsdsd
rev. 0 ad5260/ad5262 ?8? all digital inputs are protected with a series input resistor and parallel zener esd structure as shown in figure 6. this a pplies to digital input pins cs , sdi, sdo, pr , shdn , and clk. 340 logic figure 6. esd protection of digital pins a, b, w v ss figure 7. esd protection of resistor terminals layout and power supply bypassing it is a good practice to employ compact, minimum-lead length layout design. the leads to the input should be as direct as pos- sible with a minimum conductor length. ground paths should have low resistance and low inductance. similarly, it is also a good practice to bypass the power supplies with quality capacitors for optimum stability. supply leads to the device should be bypassed with 0.01 m f?.1 m f disc or chip ceram- ics capacitors. low-esr 1 m f to 10 m f tantalum or electrolytic capaci tors should also be applied at the supplies to minimize any transient disturbance (see figure 8). notice the digital ground should also be joined remotely to the analog ground to minimize the ground bounce. v ss c3 c4 c1 c2 10 f v ss v dd 0.1 f gnd v dd 0.1 f 10 f figure 8. power supply bypassing terminal voltage operating range the ad5260/ad5262 positive v dd and negative v ss power supply defines the boundary conditions for proper 3-terminal digital potentiometer operation. supply signals present on termi- nals a, b, and w that exceed v dd or v ss will be clamped by the internal forward biased diodes (see figure 9). v dd a w b v ss figure 9. maximum terminal voltages set by v dd and v ss the ground pin of the ad5260/ad5262 device is primarily used as a digital ground reference, which needs to be tied to the pcb? common ground. the digital input control signals to the ad5260/ ad5262 must be referenced to the device ground pin (gnd), and must satisfy the logic level defined in the specification table of this data sheet. an internal level shift circuit ensures that the common-mode voltage range of the three terminals extends from v ss to v dd regardless of the digital input level. power-up sequence since there are diodes to limit the voltage compliance at termi- nals a, b, and w (see figure 9), it is important to power v dd /v ss first before applying any voltage to terminals a, b, and w. other- wise, the diode will be forward biased such that v dd /v ss will be powered unintentionally and may affect the rest of the user? circuit. the ideal power-up sequence is in the following order: gnd, v dd , v ss , v l , digital inputs, and v a/b/w . the order of powering v a , v b , v w , and digital inputs is not important as long as they are powered after v dd /v ss . daisy-chain operation the serial-data output (sdo) pin contains an open drain n-channel fet. this output requires a pull-up resistor to trans- fer data to the next package? sdi pin. this allows for daisy chaining several rdacs from a single processor serial data line. the pull-up resistor termination voltage can be larger than the v dd supply voltage. it is recommended to increase the clock period when using a pull-up resistor to the sdi pin of the following device in series because capacitive loading at the daisy-chain node sdo-sdi between devices may induce time delay to subsequent devices. users should be aware of this potential problem to achieve data transfer successfully (see figure 10). if two ad5260s are daisy- chained, this requires a total of 16 bits of data. the first 8 bits, complying with the format shown in table i, go to u2, and the second 8 bits with the same format go to u1. the cs should be kept low until all 16 bits are clocked into their respective serial registers, and the cs is then pulled high to complete the opera tion. cs cl sd sd dd cs cl sd sd s c sclk ss r p 2.2k ad5260 ad5260 u1 u2 figure 10. daisy-chain configuration rdac structure the rdac contains a string of equal resistor segments, with an array of analog switches, that act as the wiper connection. the number of positions is the resolution of the device. the ad5260/ ad5262 have 256 connection points allowing it to provide better than 0.4% set-ability resolution. figure 11 shows an equivalent structure of the connections between the three terminals that make up one channel of the rdac. the sw a and sw b w ill always be on, while one of the switches sw(0) to sw(2 n ?1) will be on one at a time depending on the resistance position decoded from the data bits. since the switch is not ideal, there is a 60 w wiper resistance, r w . wiper resistance is a function of supply voltage and temperature. the lower the supply voltage, the higher the wiper resistance. similarly, the higher the temperature, the higher the wiper resistance. users should be aware of the contribution of the wiper resistance when accurate prediction of the output resistance is needed.
rev. 0 ?9? ad5260/ad5262 d7 d6 d5 d4 d3 d2 d1 d0 rdac latch and decode ax wx bx r s = r ab /2 n r s r s r s r s s hdn dlcrcr edrclr srdc programming the variable resistor rheostat operation the nominal resistances of the rdac between terminals a and b are available with values of 20 k w , 50 k w , and 200 k w . the final three digits of the part number determine the nominal resistance value, e.g., 20 k w = 20; 50 k w = 50; 200 k w = 200. the nominal resistance (r ab ) of the vr has 256 contact points accessed by the wiper terminal, plus the b terminal contact. the 8-bit data in the rdac latch is decoded to select one of the 256 possible settings. assuming a 20 k w part is used, the wiper? first connection starts at the b terminal for data 00 h . since there is a 60 w wiper contact resistance, such connection yields a minimum of 60 w resistance between terminals w and b. the second connection is the first tap point corresponds to 138 w (r wb = r ab /256 r w = 78 w 60 w ) for data 01 h . the third connection is the next tap point represent- ing 216 w (78 2 60) for data 02 h and so on. each lsb data value increase moves the wiper up the resistor ladder until the last tap point is reached at 19982 w [r ab 1 lsb r w ]. the wiper does not directly connect to the b terminal. see figure 11 for a simplified diagram of the equivalent rdac circuit. the general equation determining the digitally programmed output resistance between w and b is: rd d rr wb ab w () =+ 256 (1) where d is the decimal equivalent of the binary code which is loaded in the 8-bit rdac register, and r ab is the nominal end- to-end resistance. for example, r ab = 20 k w , when v b = 0 v and a?erminal is open circuit, the following output resistance values r wb will be set for the following rdac latch codes. the result will be the same if terminal a is tied to w: dr wb (dec) ( w )o utput state 256 19982 full-scale (r ab ?1 lsb + r w ) 128 10060 mid-scale 1 138 1 lsb 06 0 zero-scale (wiper contact resistance) note that in the zero-scale condition a finite wiper resistance of 60 w is present. care should be taken to limit the current flow between w and b in this state to no more than 20 ma to avoid degradation or possible destruction of the internal switches. like the mechanical potentiometer the rdac replaces, the ad5260/ad5262 parts are totally symmetrical. the resistance between the wiper w and terminal a also produces a digitally controlled complementary resistance r wa . figure 12 shows the symmetrical programmability of the various terminal connections. when r wa is used, the b?erminal can be let floating or tied to the wiper. setting the resistance value for r wa starts at a maximum value of resistance and decreases as the data loaded in the latch is increased in value. the general equation for this operation is: rd d rr wa ab w () = - + 256 256 (2) for example, r ab = 20 k w , when v a = 0 v and b?erminal is open, the following output resistance r wa will be set for the following rdac latch codes. the result will be the same if terminal b is tied to w: dr wa (dec) ( w )o utput state 256 60 full-scale 128 10060 mid-scale 1 19982 1 lsb 0 20060 zero-scale r wb r wa r ab = 20k d ? code in decimal 20 064128 192 256 r wa ( d), r wb ( d) k 16 12 8 4 0 figure 12. ad5260/ad5262 equivalent rdac circuit the typical distribution of the nominal resistance r ab from channel to channel matches within 1%. device-to-device match- ing is process lot dependent with the worst case of 30% variation. on the other hand, since the resistance element is processed in thin film technology, the change in r ab with temperature has a low 35 ppm/ c temperature coefficient.
rev. 0 ad5260/ad5262 ?10? code ? decimal rheostat mode inl ? lsb 0 256 ?0.2 32 64 96 128 160 192 224 ?0.1 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 5v 12v 5v 15v tpc 1. r-inl vs. code vs. supply voltages code ? decimal potentiometer mode dnl ? lsb 0 256 ?0.5 32 64 96 128 160 192 224 ?0.4 ?0.2 ?0.1 0.1 0.3 0.5 ?0.3 0 0.2 0.4 t a = 125 c t a = 85 c t a = 25 c t a = 40 c tpc 4. dnl vs. code, v dd /v ss = 5 v v dd ? v ss ? v potentiometer mode inl ? lsb 0 20 ?1.0 51015 1.0 ?0.5 0 0.5 avg +3 avg avg ?3 tpc 7. inl vs. supply voltages code ? decimal rheostat mode dnl ? lsb 0 256 ?0.25 32 64 96 128 160 192 224 ?0.20 ?0.10 ?0.05 0 0.05 0.10 ?0.15 5v 12v 5v 15v tpc 2. r-dnl vs. code vs. supply voltages code ? decimal potentiometer mode inl ? lsb 0 256 32 64 96 128 160 192 224 ?0.4 ?0.2 ?0.1 0.1 0.2 ?0.3 0 5v 0.3 15v 5v tpc 5. inl vs. code vs. supply voltages v dd ? v ss ? v rheostat mode inl ? lsb 0 20 ?2.0 51015 2.0 ?1.0 0 1.0 avg +3 avg 1.5 ?1.5 ?0.5 0.5 avg ?3 tpc 8. r-inl vs. supply voltages code ? decimal potentiometer mode inl ? lsb 0 256 ?1.0 32 64 96 128 160 192 224 ?0.8 ?0.4 ?0.2 0.2 0.6 1.0 ?0.6 0 0.4 0.8 v dd = 5v v ss = 5v r ab = 20k t a = 25 c t a = 40 c t a = 125 c t a = 85 c tpc 3. inl vs. code, v dd /v ss = 5 v code ? decimal potentiometer mode dnl ? lsb 0 256 32 64 96 128 160 192 224 ?0.5 ?0.3 ?0.2 0.1 0.3 ?0.4 ?0.1 5v 0.5 15v 5v 0.2 0.4 0 tpc 6. dnl vs. code vs. supply voltages v dd ? v wiper resistance ? 5 15 4 13 11 124 44 84 24 64 104 r on @ v dd /v ss = 5v/0v 7 r on @ v dd /v ss = 15v/0v r on @ v dd /v ss = 5v/ 5v tpc 9. wiper on resistance vs. bias voltage ?ypical performance characteristics
rev. 0 ?11? ad5260/ad5262 temperature ? c fse ? lsb ?40 100 ?2.5 ?20 20 80 0 ?2.0 ?1.0 ?1.5 ?0.5 40 v dd /v ss = +15v/0v 060 v dd /v ss = +5v/0v v dd /v ss = 5v tpc 10. full-scale error temperature ? c i logic ? a ?40 125 24.5 ?7 26 92 28.0 25.5 26.5 59 v dd /v ss = +15v/0v 25.0 26.0 27.5 v dd /v ss = 5v 27.0 tpc 13. i logic vs. temperature temperature ? c zse ? lsb ?40 100 0 ?20 20 80 2.5 0.5 1.5 1.0 2.0 40 060 v dd /v ss = +5v/0v v dd /v ss = 5v v dd /v ss = +15v/0v tpc 11. zero-scale error v ih ? v i logic ? a 0 5 10 1k 100 v dd /v ss = 5v/0v v logic = 5v v dd /v ss = 5v/0v v logic = 3v 1234 tpc 14. i logic vs. digital input voltage temperature ? c i dd /i ss supply current ? a ?40 125 0.001 ?7 26 92 1 0.01 0.1 59 v dd /v ss = 15v/0v v dd /v ss = 5v v logic = 5v v ih = 5v v il = 0v tpc 12. supply current vs. temperature code ? decimal rheostat mode tempco ? ppm/ c 0 256 ?20 80 20k 64 96 160 224 ?10 192 128 32 0 10 20 30 40 50 60 70 50k 200k tpc 15. rheostat mode tempco d r wb / d t vs. code code ? decimal potentiometer mode tempco ? ppm/ c 0 256 ?60 120 20k 64 96 160 224 ?40 192 128 32 ?20 0 20 40 60 80 100 50k 200k tpc 16. potentiometer mode d v wb / d t vs. code frequency ? hz gain ? db 1k 1m ?54 6 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 10k 100k code = ff h 01 h 02 h 04 h 08 h 10 h 20 h 40 h 80 h t a = 25 c tpc 17. gain vs. frequency vs. code, r ab = 20 k w
rev. 0 ad5260/ad5262 ?12? frequency ? hz gain ? db 1k 1m ?54 6 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 10k 100k code = ff h 01 h 02 h 04 h 08 h 10 h 20 h 40 h 80 h t a = 25 c tpc 18. gain vs. frequency vs. code r ab = 50 k w frequency ? hz normalized gain flatness ? 0.1db/div 0db 100 100k 1k 10k code = 80 h v dd /v ss = 5v t a = 25 c r = 20k r = 200k r = 50k tpc 21. normalized gain flatness vs. frequency 20mv/div 1 s/div 5v/div tpc 24. mid-scale glitch energy, code 80 h to 7f h frequency ? hz gain ? db 1k 100k ?54 6 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 10k code = ff h 01 h 02 h 04 h 08 h 10 h 20 h 40 h 80 h t a = 25 c tpc 19. gain vs. frequency vs. code r ab = 200 k w frequency ? hz i logic ? a 10k 10m 0 600 1m 100 100k 200 300 400 500 code ff h v dd /v ss = +5v/0v v dd /v ss = 5v code 55 h tpc 22. i logic vs. frequency 5v/div 20 s/div 5v/div tpc 25. large signal settling time frequency ? hz gain ? db 1k 1m ?54 6 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 10k 100k ?3db bandwidths v in = 50mv rms v dd /v ss = 5v f ?3db = 310khz, r = 20k f ?3db = 131khz, r = 50k f ?3db = 30khz, r = 200k tpc 20. ?3 db bandwidth frequency ? hz psrr ? db 100 1m 0 600 10k 100 1k 200 300 400 500 100k ?psrr @ v dd = 5v dc 10% p-p ac + psrr @ v dd = 5v dc 10% p-p ac code = 80 h , v a = v dd , v b = 0v tpc 23. psrr vs. frequency 10mv/div 40ns/div tpc 26. digital feedthrough vs. time
rev. 0 ?13? ad5260/ad5262 code ? decimal theoretical i wb_max ? ma 0 256 0.01 100 0.1 1 10 32 64 96 128 160 192 224 r ab = 200k v a = v b = open t a = 25 c r ab = 50k r ab = 20k tpc 27. i max vs. code hours of operation at 150 c change in terminal resistance ? % 0 500 ?0.20 0.10 ?0.10 0 0.05 100 200 250 300 350 400 450 avg ?3 code = 80 h v dd = v ss = 5v ss = 135 units 50 150 ?0.05 ?0.15 avg +3 avg tpc 28. long-term resistance drift channel-to-channel r ab match ? % frequency ?0.50 0 40 30 code set to mid-scale t a = 150 c 3 lots sample size = 135 20 10 ?0.40 ?0.30 ?0.20 ?0.10 0 0.10 0.20 tpc 29. channel-to-channel resistance matching (ad5262) v ms a w b dut v v+ = v dd 1lsb = v+/2 n test circuit 1. potentiometer divider nonlinearity error (inl, dnl) nc i w v ms a w b dut nc = no connect test circuit 2. resistor position nonlinearity error (rheostat operation; r-inl, r-dnl) v ms1 i w = v dd /r nominal v ms2 v w r w = [v ms1 ? v ms2 ]/i w a w b dut test circuit 3. wiper resistance v ms % v dd % pss (%/%) = v+ = v dd 10% psrr (db) = 20 log v ms v dd ( ) v dd v a v ms a w b v+ test circuit 4. power supply sensitivity (pss, pssr) +13v ?13v w a b v out offset gnd dut ad8610 v in test circuit 5. gain vs. frequency w b v ss to v dd dut i sw code = 00 h r sw = 0.1v i sw 0.1v a = nc test circuit 6. incremental on resistance w b v cm i cm a nc gnd nc v ss v dd dut test circuit 7. common-mode leakage current test circuits test circuits 1 to 9 define the test conditions used in the product specification table.
rev. 0 ?14? ad5260/ad5262 test circuits (continued) sdi clk cs lc lc dlnp le c lc cd c c nc nd nc ss dd d c c programming the potentiometer divider voltage output operation the digital potentiometer easily generates output voltages at wiper- to-b and wiper-to-a to be proportional to the input voltage at a-to-b. ignore the effect of the wiper resistance at the moment. for example, connecting a-terminal to 5 v and b-terminal to ground produces an output voltage at the wiper-to-b starting at zero volts up to 1 lsb less than 5 v. each lsb of voltage is equal to the voltage applied across terminal ab divided by the 256 posi- tion of the potentiometer divider. since the ad5260/ad5262 operates from dual supplies, the general equation defining the output voltage at v w with respect to ground for any given input voltage applied to terminals ab is: vd d vv wabb () =+ 256 (3) operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. unlike the rheostat mode, the output voltage is dependent on the ratio of the internal resistors r wa and r wb and not the absolute values; therefore, the drift reduces to 5 ppm/ c. applications bipolar dc or ac operation from dual supplies the ad5260/ad5262 can be operated from dual supplies en abling control of ground referenced ac signals or bipolar operation. t he ac signal, as high as v dd /v ss , can be applied directly across terminals a b with output taken from terminal w. see figure 13 for a typical circuit connection. v ss +5.0v clk cs nd dd sd nd dd scl s c ss 5v p-p 2.5v p-p d = 80 h figure 13. bipolar operation from dual supplies gain control compensation digital potentiometers are commonly used in gain control as in the noninverting gain amplifier shown in figure 14. u1 v o w b a r2 200k c2 4.7pf v i r1 47k c1 25pf figure 14. typical noninverting gain amplifier notice that when the rdac b terminal parasitic capacitance is connected to the op amp noninverting node, it introduces a zero for the 1/ b o term with +20 db/dec, whereas a typical op amp gbp has ?0 db/dec characteristics. a large r2 and finite c1 can cause this zero? frequency to fall well below the crossover frequency. hence the rate of closure becomes 40 db/dec and the system has 0 phase margin at the crossover frequency. the output may ring or oscillate if the input is a rectangular pulse or step function. similarly, it is also likely to ring when switching between two gain values because this is equivalent to a step change at the input. depending on the op amp gbp, reducing the feedback resistor may extend the zero? frequency far enough to overcome the prob- lem. a better approach, however, is to include a compensation capacitor c2 to cancel the effect caused by c1. optimum compen- sation occurs when r1 c1 = r2 c2. this is not an option because of the variation of r2. as a result, one may use the relation- ship above and scale c2 as if r2 is at its maximum value. doing so may overcompensate and compromise the performance slightly when r2 is set at low values. however, it will avoid the ringing or oscillation at the worst case. for critical applications, c2 should be found empirically to suit the need. in general, c2 in the range of a few pf to no more than a few tenths of pf is usually adequate for the compensation. similarly, there are w and a terminal capacitances connected to the output (not shown). fortunately their effect at this node is less significant, and the compensation can be avoided in most cases. programmable voltage reference for voltage divider mode operation, figure 15, it is common to buffer the output of the digital potentiometer unless the load is much larger than r wb . not only does the buffer serve the pur- pose of impedance conversion, but it also allows a heavier load to be driven.
rev. 0 ?15? ad5260/ad5262 a1 v o 5v v in gnd v out 5v ad1582 u1 ad8601 1 2 3 a w b ad5260 figure 15. programmable voltage reference 8-bit bipolar dac figure 16 shows a low cost 8-bit bipolar dac. it offers the same number of adjustable steps but not the precision of conventional dacs. the linearity and temperature coefficients, especially at low values codes, are skewed by the effects of the digital potentiometer wiper resistance. the output of this circuit is: v d v o ref =- ? ? ? 2 256 1 (4) 5v ref op2177 a2 ?5v op2177 ba w w1 a1 v o +5v ?5v +5v u2 +5v ref v in gnd v out trim ad5260 v i adr425 r r u1 figure 16. 8-bit bipolar dac bipolar programmable gain amplifier for applications that require bipolar gain, figure 17 shows one implementation. digital potentiometer u1 sets the adjustment range. the wiper voltage at w2 can therefore be programmed between v i and ?v i at a given u2 setting. configuring a2 in the noninverting mode allows linear gain and attenuation. the transfer function is: v v r r d kk o i =+ ? ? ? + () - ? ? ? 1 2 1 2 256 1 (5) where k is the ratio of r wb1 /r wa1 set by u1. ?kv i a1 b1 op2177 a2 v dd v ss r1 r2 v dd v ss op2177 a2 b2 w2 u2 ad5262 u1 ad5262 w1 a1 v i v o c1 figure 17. bipolar programmable gain amplifier similar to the previous example, in the simpler (and much more usual) case, where k = 1, a single digital pot ad5260, and u1 is replaced by a matched pair of resistors to apply v i and v i at the ends of the digital pot. the relationship becomes: v r r d v oi =+ ? ? ? - ? ? ? 1 2 1 22 256 1 (6) if r2 is large, a few picofarad compensation capacitors may be needed to avoid any gain peaking. table viii shows the result of adjusting d, with a2 configured as a unity gain, a gain of 2, and a gain of 10. the result is a bipolar amplifier with linearly programmable gain and 256-step resolution. table viii. result of bipolar gain amplifier dr1 = ? , r2 = 0 r1 = r2 r2 = 9r1 01 2 ?0 64 ?.5 ? ? 128 0 0 0 192 0.5 1 5 255 0.968 1.937 9.680 programmable voltage source with boosted output for applications that require high current adjustment such as a laser diode driver or turnable laser, a boosted voltage source can be considered (see figure 18). v i a1 v o w u1 a b c c 5v signal lo n1 r1 10k p1 r bias i l u1= ad5260 a1= ad8601, ad8605, ad8541 p1= fdp360p, nds9430 n1= fdv301n, 2n7002 figure 18. programmable boosted voltage source in this circuit, the inverting input of the op amp forces the v o to be equal to the wiper voltage set by the digital potentiometer. the load current is then delivered by the supply via the p-ch fet p1. the n-ch fet n 1 simplifies the op amp driving requirement. a1 needs to be the rail-to-rail input type. resistor r1 is needed to prevent p1 from not turning off once it is on. the choice of r1 is a balance between the power loss of this resistor and the output turn- off time. n1 can be any general-purpose signal fet; on the other hand, p1 is driven in the saturation state, and therefore its power handling must be adequate to dissipate (v i ?v o ) i l power. this circuit can source a maximum of 100 ma at 5 v supply. higher current can be achieved with p1 in a larger package. note, a single n-ch fet can replace p1, n1, and r1 altogether. however, the out- put swing will be limited unless separate power supplies are used. for precision application, a voltage reference such as adr423, adr292, and ad1584 can be applied at the input of the digital potentiometer. programmable 4-to-20 ma current source a programmable 4-to-20 ma current source can be implemented with the circuit shown in figure 19. ref191 is a unique low supply headroom and high current handling precision reference
rev. 0 ?16? ad5260/ad5262 that can deliver 20 ma at 2.048 v. the load current is simply the voltage across terminals b-to-w of the digital pot divided by r s . i vd r l ref s = (7) ?5v v out op1177 + ? u2 +5v r l 100 r s 102 v l i l a b w ad5260 c1 1 f gnd ref191 sleep n 5v 2u1 3 4 6 0 to (2.048 v l ) ?2.048v to v l figure 19. programmable 4-to-20 ma current source the circuit is simple, but be aware that dual-supply op amps are ideal because the ground potential of ref191 can swing from ?.048 v at zero scale to v l at full scale of the potentiometer setting. although the circuit works under single supply, the pro- grammable resolution of the system will be reduced. programmable bidirectional current source for applications that require bidirectional current control or higher voltage compliance, a howland current pump can be a solution (see figure 20). if the resistors are matched, the load current is: i ra rb r rb v lw = + () 221 2 / (8) ?5v +5v ad8016 ?15v +15v ?15v op2177 ad5260 a1 v l w a b c2 10pf i l r1 150k r1 150k a2 c1 10pf r2 15k r2a 14.95k r l 500 r l 50 +15v figure 20. programmable bidirectional current source programmable low-pass filter digital potentiometer ad5262 can be used to construct a second order sallen key low-pass filter (see figure 21). the design equations are: v v s q s o i o o o = ++ w w w 2 2 2 (9) w o rr cc = 1 1212 (10) q rc r c =+ 1 11 1 22 (11) users can first select some convenient values for the capacitors. to achieve maximally flat bandwidth where q = 0.707, let c1 be twice the size of c2 and let r1 = r2. as a result, users can adjust r1 and r2 to the same settings to achieve the desirable bandwidth. a b v i ad8601 +2.5v v o ?2.5v w r r2 r1 a b w r c1 c2 adjusted to same settings figure 21. sallen key low-pass filter programmable oscillator in a classic wien-bridge oscillator, figure 22, the wien network (r, r ? , c, c ? ) provides positive feedback, while r1 and r2 provide negative feedback. at the resonant frequency, f o , the overall phase shift is zero, and the positive feedback causes the circuit to oscillate. with r = r ? , c = c ? , and r2 = r2a//(r2b+ r diode ), the oscillation frequency is: w p oo rc f rc == 11 2 or (12) where r is equal to r wa such that: r d r ab = 256 256 (13) at resonance, setting r r 2 1 2 = (14) balances the bridge. in practice, r2/r1 should be set slightly larger than 2 to ensure the oscillation can start. on the other hand, the alternate turn-on of the diodes d1 and d2 ensures r2/r1 to be smaller than 2 momentarily and therefore stabilizes the oscillation. once the frequency is set, the oscillation amplitude can be tuned by r2b since: 2 3 2 virbv od d =+ (15)
rev. 0 ?17? ad5260/ad5262 v o , i d , and v d are interdependent variables. with proper selection of r2b, an equilibrium will be reached such that v o converges. r2b can be in series with a discrete resistor to increase the amplitude, but the total resistance cannot be too large to saturate the output. in both circuits in figures 21 and 22, the frequency tuning requires that both rdacs be adjusted to the same settings. since the two channels will be adjusted one at a time, an intermediate state will occur that may not be acceptable for certain applications. as a result, different devices can also be used in daisy-chained mode so that parts can be programmed to the same setting simultaneously. +5v op1177 v o ?5v r2a 2.1k d1 d2 r2b 10k vn r1 1k a b w r1 = r1 = r2b = ad5262 d1 = d2 = 1n4148 ad5262 c 2.2nf r 10k ab w vp c 2.2nf frequency adjustment r 10k a b w u1 amplitude adjustment figure 22. programmable oscillator with amplitude control resistance scaling the ad5260/ad5262 offer 20 k w , 50 k w , and 200 k w nominal resistance. for users who need lower resistance and still maintain the numbers of step adjustment, they can parallel multiple devices. for example, figure 23 shows a simple scheme of paralleling both channels of the ad5262. to adjust half of the resistance linearly per step, users need to program both channels coherently with the same settings. w1 a1 b1 w2 a2 b2 ld v dd figure 23. reduce resistance by half with linear adjustment characteristics in voltage divider mode, a much lower resistance can be achieved by paralleling a discrete resistor as shown in figure 24. the equiva- lent resistance becomes: r d rr r wb eq w _ = () + 256 12 (16) r d rr r wa eq w _ =- ? ? ? () + 1 256 12 (17) w a b r2 r1 r2 << r1 figure 24. lowering the nominal resistance figures 23 and 24 show that the digital potentiometers change steps linearly. on the other hand, log taper adjustment is usually pre- ferred in applications like audio control. figure 25 shows another way of resistance scaling. in this circuit, the smaller the r2 with respect to r ab , the more the pseudo-log taper characteristic be haves. v o a b r1 r2 v i w figure 25. resistor scaling with log adjustment characteristics rdac circuit simulation model the internal parasitic capacitances and the external capacitive loads dominate the ac characteristics of the rdacs. configured as a potentiometer divider, the ? db bandwidth of the ad5260 (20 k w resistor) measures 310 khz at half scale. tpc 20 provides the large signal bode plot characteristics of the three available resistor versions 20 k w , 50 k w , and 200 k w . a parasitic simulation model is shown in figure 26. listing i provides a macro model net list for the 20 k w rdac. ab 55pf c a 25pf c b 25pf c w rdac 20k w figure 26. rdac circuit simulation model for rdac = 20 k w listing i. macro model net list for rdac param d=256, rdac=20e3 * subckt dpot (a,w,b) * ca a 0 25e-12 rwa a w {(1-d/256) * rdac+60} cw w 0 55e-12 rwb w b {d/256 * rdac+60} cb b 0 25e-12 * .ends dpot
rev. 0 C18C ad5260/ad5262 digital potentiometer family selection guide 1 number terminal interface nominal resolution power supply part of vrs per voltage data resistance (no. of wiper current number package range (v) control (k ) positions) (i dd ) ( a) packages comments ad5201 1 3, 5.5 3-wire 10, 50 33 40 m soic-10 full ac specs, dual supply, power-on- reset, low cost ad5220 1 5.5 up/down 10, 50, 100 128 40 pdip, so-8, no rollover, m soic-8 power-on-reset ad7376 1 15, 28 3-wire 10, 50, 100, 128 100 pdip-14, single 28 v or dual 1000 sol-16, 15 v supply operation tssop-14 ad5200 1 3, 5.5 3-wire 10, 50 256 40 m soic-10 full ac specs, dual supply, power-on-reset ad8400 1 5.5 3-wire 1, 10, 50, 100 256 5 so-8 full ac specs ad5260 1 5, 15 3-wire 20, 50, 200 256 60 tssop-14 5 v to 15 v or 5 v operation, tc < 50 ppm/ c ad5241 1 3, 5.5 2-wire 10, 100, 256 50 so-14, i 2 c compatible, 1000 tssop-14 tc < 50 ppm/ c ad5231 1 2.75, 5.5 3-wire 10, 50, 100 1024 20 tssop-16 nonvolatile memory, direct program, i/d, 6 db settability ad5222 2 3, 5.5 up/down 10, 50, 100, 128 80 so-14, no rollover, stereo, 1000 tssop-14 power-on-reset, tc < 50 ppm/ c ad8402 2 5.5 3-wire 1, 10, 50, 256 5 pdip, so-14, full ac specs, na 100 tssop-14 shutdown current ad5207 2 3, 5.5 3-wire 10, 50, 100 256 40 tssop-14 full ac specs, dual supply, power-on- reset, sdo ad5232 2 2.75, 5.5 3-wire 10, 50, 100 256 20 tssop-16 nonvolatile memory, direct program, i/d, 6 db settability ad5235 2 2 2.75, 5.5 3-wire 25, 250 1024 20 tssop-16 nonvolatile memory, direct program, tc < 50 ppm/ c ad5242 2 3, 5.5 2-wire 10, 100, 256 50 so-16, i 2 c compatible, 1000 tssop-16 tc < 50 ppm/ c ad5262 2 5, 15 3-wire 20, 50, 200 256 60 tssop-16 5 v to 15 v or 5 v operation, tc < 50 ppm/ c ad5203 4 5.5 3-wire 10, 100 64 5 pdip, sol-24, full ac specs, na tssop-24 shutdown current ad5233 4 2.75, 5.5 3-wire 10, 50, 100 64 20 tssop-24 nonvolatile memory, direct program, i/d, 6 db settability ad5204 4 3, 5.5 3-wire 10, 50, 100 256 60 pdip, sol-24, full ac specs, dual tssop-24 supply, power-on-reset ad8403 4 5.5 3-wire 1, 10, 50, 100 256 5 pdip, sol-24, full ac specs, na tssop-24 shutdown current ad5206 6 3, 5.5 3-wire 10, 50, 100 256 60 pdip, sol-24, full ac specs, dual tssop-24 supply, power-on-reset 1 for the most current information on digital potentiometers, check the website at: www.analog.com/digitalpotentiometers 2 future product, consult factory for latest status.
rev. 0 ?19? ad5260/ad5262 14-lead tssop (ru-14) 14 8 7 1 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 0.201 (5.10) 0.193 (4.90) seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0 16-lead tssop (ru-16) 16 9 8 1 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 0.201 (5.10) 0.193 (4.90) seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0 outline dimensions dimensions shown in inches and (mm).
?20? c02695?0?3/02(0) printed in u.s.a.

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